The CoreGen Intermediate Representation (IR) specification governs the permissible YAML syntax in the CoreGen IR. The CoreGen IR is utilized as the central point of focus for user interfaces and the CoreGen pass infrastructure.
| Version | Changelog | Link |
|---|---|---|
| 1.4.5 2020-04-28 | Adding LineSize cache line size parameter and memory or- dering parameters; Adding read and write ports to register classes; Adding DataPath nodes; Adding RegIsDestination keyword to instruction formats | CoreGenIR Version 1.4.5 |
| 1.4.4 2019-08-27 | Adding notes syntax to each candidate IR node | CoreGenIR Version 1.4.4 |
| 1.4.3 2019-08-21 | Adding syntax mnemonics to pseudo instructions | CoreGenIR Version 1.4.3 |
| 1.4.2 2019-07-03 | Adding Override keyword to all candidate hardware nodes: Section 2.3 | CoreGenIR Version 1.4.2 |
| 1.4.1 2019-04-24 | Adding PC attribute to register node attributes | CoreGenIR Version 1.4.1 |
| 1.4 2019-01-21 | Adding RTL Type fields for overloaded RTL models; Adding Syntax mnemonic fields for instructions | CoreGenIR Version 1.4 |
| 1.3 2018-12-20 | Adding text to describe the IR node naming convention with appropriate examples | CoreGenIR Version 1.3 |
| 1.2 2018-11-21 | Adding ThreadUnits to Core nodes and TUSReg register attributes; Adding subregister pseduoregister sub-node structure for setting up register aliases to specific bit regions of parent registers | CoreGenIR Version 1.2 |