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We have officially released updates to the CoreGen IR Spec and the StoneCutter Language Spec. The CoreGen IR Spec update (1.4.5) adds new parameters for cache nodes, memory controllers and register nodes. It also adds a new node type, “DataPath”, designed to help define a core’s pipeline structure. The StoneCutter Language Spec (0.6) adds a new pipeline syntax to define pipeline stages for each instruction and across instructions. It also adds a full set of register attributes and updates to the “for” loop syntax. Check out the System Architect release pages for the full specs!

The CoreGen Intermediate Representation (IR) specification version 1.4.2 has been released!  Note that this released is still considered a DRAFT as we have many features planned to implement for the forthcoming months.

You can download the latest IR specs on the CoreGen IR Release page.

You can find the source code for the spec on Github.  Feel free to make comments/questions via the Github Issues.  See the IR spec Github source URL on list of repositories.

The latest updates to the CoreGen IR Spec and the StoneCutter Language spec have been released. The latest update permits users to define registers in the CoreGen IR that are designated as program counters (PC). The StoneCutter language also allows users to add this “PC” attribute to registers. The downstream affect of these changes permits the code generation mechanisms to accurately generate signals to automatically update the appropriate signals.

You can find the latest updates to the specs on the respective release pages.

The second System Architect tutorial lesson has officially been released. This lesson (Level 2) outlines the implementation concepts associated with building instructions in the StoneCutter language and its associated tools. Users/readers will utilize the BasicRISC design constructed in the Level 1 tutorial as the basis for the new material. At the end of this lesson, users will have the full definition for all the included BasicRISC instructions in the StoneCutter language.

For more information, see the System Architect tutorials page.

The second public draft of the StoneCutter language specification has been released. Version 0.2 presents the initial StoneCutter Language, the overall design flow, intrinsic circuit functions and a sample ISA written in StoneCutter. This release also allows users to directly associated instruction definitions with instruction formats.

You can download the draft 0.2 release from the StoneCutter Language Specification Release page.

You can find the source code for the spec on Github. Feel free to make comments/questions via the Github Issues. See the language spec Github source URL on our list of repositories.

The first public draft of the StoneCutter language specification has been released. Version 0.1 presents the initial StoneCutter Language, the overall design flow, intrinsic circuit functions and a sample ISA written in StoneCutter.

You can download the draft 0.1 release from the StoneCutter Language Specification Release page.

You can find the source code for the spec on Github.  Feel free to make comments/questions via the Github Issues.  See the language spec Github source URL on our list of repositories.

The CoreGen Intermediate Representation (IR) specification version 1.4 has been released!  Note that this released is still considered a DRAFT as we have many features planned to implement for the forthcoming months.

You can download the latest IR specs on the CoreGen IR Release page.

You can find the source code for the spec on Github.  Feel free to make comments/questions via the Github Issues.  See the IR spec Github source URL on list of repositories.

The CoreGen Intermediate Representation (IR) specification version 1.3 has been released!  Note that this released is still considered a DRAFT as we have many features planned to implement for the forthcoming months.

You can download the latest IR specs on the CoreGen IR Release page.

You can find the source code for the spec on Github.  Feel free to make comments/questions via the Github Issues.  See the IR spec Github source URL on list of repositories.

The first set of System Architect tutorials have been officially posted to Github.  The tutorial includes design input files, slides and a sample RISC processor developed in a simple, concise format.  The design files are licensed under an Apache2 license such that they can be extended and utilized by developers for their own System Architect projects.  

You can find the tutorial material here.  

The CoreGen Intermediate Representation (IR) specification version 1.2 has been released!  Note that this released is still considered a DRAFT as we have many features planned to implement for the forthcoming months.

You can download the latest IR specs on the CoreGen IR Release page.

You can find the source code for the spec on Github.  Feel free to make comments/questions via the Github Issues.  See the IR spec Github source URL on list of repositories.