Open Source SoC Development Workflow
The CoreGen Intermediate Representation (IR) specification version 1.3 has been released! Note that this released is still considered a DRAFT as we have many features planned to implement for the forthcoming months.
You can download the latest IR specs on the CoreGen IR Release page.
You can find the source code for the spec on Github. Feel free to make comments/questions via the Github Issues. See the IR spec Github source URL on list of repositories.
The first set of System Architect tutorials have been officially posted to Github. The tutorial includes design input files, slides and a sample RISC processor developed in a simple, concise format. The design files are licensed under an Apache2 license such that they can be extended and utilized by developers for their own System Architect projects.
You can find the tutorial material here.
The CoreGen Intermediate Representation (IR) specification version 1.2 has been released! Note that this released is still considered a DRAFT as we have many features planned to implement for the forthcoming months.
You can download the latest IR specs on the CoreGen IR Release page.
You can find the source code for the spec on Github. Feel free to make comments/questions via the Github Issues. See the IR spec Github source URL on list of repositories.